1. Field of the Invention
The present invention relates to a circuit structure of a pixel region of an active matrix type display device using thin-film transistors, and particularly to a structure of an auxiliary capacitor.
2. Description of the Related Art
In recent years, a technique for manufacturing thin-film transistors (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for active matrix type liquid crystal display devices has been increased.
In the active matrix type liquid crystal display device, thin-film transistors are respectively arranged for each of several tens to several million pixels arranged in matrix form to control electrical charge going in and out of the respective pixel electrodes by a switching function of the thin-film transistor.
A liquid crystal is placed between the respective pixel electrodes and opposing electrodes so that a kind of capacitor is formed. Accordingly, if going in and out of electrical charge to the capacitor is controlled by the thin-film transistor, the electro-optical characteristics of the liquid crystal are changed so that a picture image can be displayed by controlling light transmitting through a liquid crystal panel.
The capacitor having such a structure has a problem that since a hold voltage of the capacitor is gradually decreased by a leak current, the electro-optical characteristics of the liquid crystal is changed so that the contrast of display of a picture image is deteriorated.
Then, such a structure becomes common that another capacitor referred to as an auxiliary capacitor is disposed in series with the capacitor constituted by the liquid crystal so that electrical charge lost through a leak or the like is supplied to the capacitor constituted by the liquid crystal.
FIG. 4 is a circuit diagram showing a conventional active matrix type liquid crystal display device. The active matrix type liquid crystal display circuit is roughly divided into three parts. That is, the circuit is divided into a gate driver circuit 62 for driving gate wiring lines (scan wiring lines) 64, a data driver circuit 61 for driving data wiring lines (source wiring lines, signal wiring lines), and an active matrix circuit 63 in which pixels are provided. Among them, the data driver circuit 61 and the gate driver circuit 62 are generally referred to as a peripheral circuit.
In the active matrix circuit 63, a number of gate wiring lines 64 and data wiring lines 65 are provided so as to cross with each other, and pixel electrodes 67 are provided at each intersection point. Further, a switching element (thin-film transistor) 66 for controlling electrical charge going in and out of the pixel electrode is provided. Still further, as described above, in order to suppress the change of a voltage of a pixel due to the leak current, an auxiliary capacitor 68 is provided in parallel with a capacitor of the pixel (FIG. 4).
Various methods of forming an auxiliary capacitor have been proposed, and the most typical structure of the auxiliary capacitor uses the overlap of an active layer (semiconductor layer) of a thin-film transistor and a gate wiring line.
FIGS. 3A to 3E show the state of a cross section of an active matrix type circuit using top-gate type thin-film transistors, while explaining the manufacturing steps. An intrinsic active layer 42 is formed on a substrate 41, and is selectively doped with N-type or P-type impurities to form a conductive region 44. Further, a gate insulating film 43 is formed so as to cover the active layer, and gate wiring lines 45 and 46 are formed (FIG. 3A).
In general, the gate wiring lines 45 and 46 use wiring lines in rows different from each other. In the pixel shown in the drawing, the gate wiring line 45 functions as a gate electrode of the thin-film transistor, and the gate wiring 46 functions as an electrode of an auxiliary capacitor 49. The reason why the wiring lines in the different rows are used is that if the gate wiring lines 45 and 46 are those in the same row, parasitic capacitance between a drain and the gate electrode of the thin-film transistor becomes extremely large, so that it constitutes an obstacle to a switching function. In the drawing, the gate wiring 46 is for constituting the auxiliary capacitor, and another wiring line for only increasing an aperture ratio is not generally formed.
Next, impurities having the same conductivity as the conductive region 44 are implanted while using the gate electrode as a mask so that a source 47 and a drain 48 are formed in a self-alignment manner. In this way, the auxiliary capacitor 49 is formed between the gate wiring line 46, and the conductive region 44 and the drain 48 (FIG. 3B).
Thereafter, a first interlayer insulator including a silicon nitride layer 50 as a passivation film and a layer 51 of a material suitable for flattening such as polyimide, is formed and is etched so that a contact hole reaching to the source 47 is formed. Then, a data wiring line 52 is provided (FIG. 3C).
Since the conductivity of the thin-film transistor is varied by irradiation of light, in order to prevent the variation, a coating film (black matrix) 54 having light shielding properties is overlapped on the thin-film transistor. Further, in order to prevent mixing of colors and degrees of brightness between pixels and to prevent poor display due to the disturbance of an electric field at boundary portions of the pixels, the above light shielding coating film is also formed between pixels. Thus, the light shielding coating film has a matrix shape so that it is called a black matrix (BM). The BM 54 is formed on a second interlayer insulator 53 (FIG. 3D).
Thereafter, a third interlayer insulator 55 is formed, and is etched to form a contact hole reaching to the drain 48 (or conductive region 44). Further, a pixel electrode 56 is formed of a transparent conductive coating film. If the BM is formed of an insulating material, the third interlayer insulator 55 is not necessary (FIG. 3E).
Among the above steps, main steps are enumerated as follows.
A forming step of the active layer 42 PA0 B selective doping step for forming the conductive region 44 PA0 C forming step of the gate insulating film 43 PA0 D forming step of the gate wiring lines 45 and 46 PA0 E self-alignment doping step for forming the source 47 and the drain 48 PA0 F forming step of the first interlayer insulators 50 and 51 PA0 G forming step of the contact hole PA0 H forming step of the data wiring line 52 PA0 I forming step of the second interlayer insulator 53 PA0 J forming step of the black matrix 54 PA0 K forming step of the third interlayer insulator 55 PA0 L forming step of the contact hole PA0 M forming step of the pixel electrode 56 PA0 A forming step of the active layer 42 PA0 B' selective doping step for forming the conductive region 44, source 47, and drain 48 PA0 C forming step of the gate insulating film 43 PA0 D forming step of the gate wiring lines 45 and 46 (there is no step corresponding to step E) PA0 F forming step of the first interlayer insulators 50 and 51 PA0 G forming step of the contact hole PA0 H forming step of the data wiring line 52 PA0 I forming step of the second interlayer insulator 53 PA0 J forming step of the black matrix 54 PA0 K forming step of the third interlayer insulator 55 PA0 L forming step of the contact hole PA0 M forming step of the pixel electrode 56 PA0 a forming step of an active layer (there is no step corresponding to step B) PA0 c forming step of a gate insulating film PA0 d forming step of a gate wiring line PA0 e self-alignment doping step for forming a source and a drain (conductive region) PA0 f forming step of a first interlayer insulator (containing a silicon nitride layer) PA0 g forming step of a contact hole PA0 h forming step of a data wiring line PA0 i forming step of a second interlayer insulator PA0 x etching step of a hole for an auxiliary capacitor PA0 j forming step of a black matrix PA0 k forming step of a third interlayer insulator PA0 l forming step of a contact hole PA0 m forming step of a pixel electrode
Among the above steps, eight steps A, B, D, G, H, J, L and M are accompanied by a photolithography step.
FIGS. 10A to 10D show the state of a cross section of an active matrix circuit using bottom-gate type thin-film transistors while explaining the manufacturing steps. A gate wiring line 172 and a capacitor wiring line 173 are formed on a substrate 171. The capacitor wiring line 173 may also serves as a gate wiring line, and in this case, an opening region can be made large as compared with the case where the capacitor wiring line is especially provided.
In the case where the capacitor wiring line 173 is used as the gate wiring line, the wiring line of a row different from the gate wiring line 172 is used. If the gate wiring line 172 and the wiring line 173 are in the same row, parasitic capacitance between the drain and the gate electrode of the thin-film transistor becomes extremely large, so that switching is hindered.
Incidentally, in the case where the capacitor wiring line 173 serves also as the gate wiring line, there is also such a defect that the parasitic capacitance of the wiring line becomes large so that the operation speed slows down and the signal shape becomes dull.
Next, a gate insulating film 174 covering these wiring lines, and an intrinsic semiconductor layer 175 are formed. Further, conductive regions (source, drain) 176 and 177, which are doped with N-type or P-type impurities and are connected to the semiconductor layer 175, are formed. Further, a data wiring line 178 is formed (FIG. 10A).
In this way, an auxiliary capacitor 179 including the gate insulating film 174 as a dielectric is obtained between the capacitor wiring line 173 and the conductive region 177.
Thereafter, a first interlayer insulator including a silicon nitride film 180 as a passivation film and a layer 181 made of a resin material suitable for flattening, such as polyimide, is formed (FIG. 10B).
Since the conductivity of the thin-film transistor is changed by irradiation of light, in order to prevent the variation, a coating film (black matrix) 182 having light shielding properties is overlapped on the thin-film transistor. Further, in order to prevent the mixture of colors and degrees of brightness between pixels and to prevent poor display due to the disturbance of an electric field at boundary portions of the pixels, the above light shielding coating film is also formed between the pixels. Thus, the light shielding coating film has a matrix shape so that it is called a black matrix (BM). If the BM 182 is formed on the substrate on which the active matrix circuit is provided, it has an effect in integration of pixels. In this case, the BM 182 is formed on the polyimide layer 181 of the first interlayer insulator (FIG. 10C).
Thereafter, a second interlayer insulator 183 is formed. The second and the first interlayer insulators are etched to form a contact hole reaching to the conductive region 177. Further, pixel electrodes 184 and 185 (pixel electrodes of other pixels) are formed of a transparent conductive coating film. In general, the BM and the pixel electrodes are formed so as not to form a portion where they are not overlapped with each other. If the BM 182 is formed of an insulating material, the second interlayer insulator 183 is not necessary (FIG. 10D).
The active matrix circuit of the above structure has a feature that since the gate insulating film having a high withstand voltage can be used as an insulator (dielectric) of the auxiliary capacitor, large capacitance can be obtained.
However, in some cases, the capacitance is insufficient. In order to increase the auxiliary capacitance, the area occupied by the capacitor wiring line must be increased. That is, according to a conventional method, the auxiliary capacitor has a main structure of two-dimensional extension. However, since the portion where the capacitor wiring line is disposed, does not transmit light, an opening rate is lowered.
Further, the conventional method has a defect that since the gate wiring also serves as the electrode of the auxiliary capacitor, the parasitic capacitance of the wiring line becomes large, so that the operation speed slows down and the signal shape becomes dull. With respect to this defect, there is a method in which the gate wiring line and the wiring line of the auxiliary capacitor are separately provided. However, as described above, the area occupied by the wiring lines is increased by that, so that the opening rate is lowered.
The present invention intends to solve these problems and to increase auxiliary capacitance by constituting an auxiliary capacitor in three-dimension without lowering an aperture ratio.
Further, the active matrix circuit using top-gate type thin-film transistors has such a defect that two doping steps are necessary, and a photolithography step is necessary to define a doping region for the purpose of forming the conductive region 44.
With respect to this defect, if doping of the source and drain is also carried out in the stage of the above step B, the number of doping steps can be made one. However, in that case, a self-alignment type transistor can not be made, parasitic capacitance is large, and there is a fear that the parasitic capacitance would vary for each transistor. Further, also in this case, the photolithography step at doping is necessary.
The steps of this improved conventional method are as follows.
Among the above steps, eight steps A, B, D, G, H, J, L and M are accompanied by the photolithography step.